As is known, in order to select a generic cell of the memory matrix, for example, during the reading step, it is necessary to select the row to which the cell belongs applying a pre-established potential to a corresponding row line or word line. Similarly, the matrix column corresponding to the cell is selected by a selector or multiplexer which enables a column line (bit line), so connecting it to a reading circuit with which it is possible to read the data contained in the cell, for example performing a current type reading.
In the case of a non-volatile type memory composed of a NOR type cell matrix, the multiplexer accesses one, and just one, bit line for each cell selected. Generally, said multiplexer is made of multi-line structures which select, by means of MOS transistors, the pre-established bit line among a plurality of column lines. The gate terminal of the transistors used in the multiplexer is connected to a respective command line to which a voltage level signal, suitable to enable or disable the transistor itself, is sent. The voltage signal present on each command line is obtained by decoding an address signal. Given the great number of cells present in a matrix, the multi-line structures are arranged on various levels and the current which passes through the transistors of the multiplexer, during reading, produce voltage drops along the path from the reading circuit to the cell. In the case of NOR cells, the path of the current is not long and, consequently, the impedance on the drain terminal of the cell is not high.
If the matrix is composed of NROM type cells, a multiplexer, also in this case composed of transistors arranged on multi-line structures, always selects two different bit lines to access and read each cell. This is due to the particular way in which a NROM cell can be programmed or read. In particular, the NROM memory cells taken into consideration are dual bit cells where it is possible to store one bit for each side of the cell. The NROM dual bit cell 1, illustrated schematically in FIG. 1, has a p−-type doped channel 2 disposed between two n+-type regions, 3 and 4, which is accessed through the two bit lines selected by the multiplexer. The cell also comprises two areas 5 and 6, each of which can store an electric charge which defines one bit. In the dual bit cell 1, the areas 5 and 6 are within a nitride layer 7 interposed between a first oxide layer 8 and a second oxide layer 9, on which a polysilicon layer 10, corresponding to a gate terminal G, is disposed.
In order to program a first bit disposed in area 6, the region 3 (connected to a bit line) represents a drain region D, and the region 4 (connected to the other bit line) represents a source region SR. In order to program a second bit disposed in area,5, the region 4 represents a drain region D and the region 3 represents a source region SR.
In order to program the first bit disposed in area 6, a pre-established voltage (for example 9V) is applied to the gate G of the cell 1. Later, a pre-established programming voltage (for example 5V) is applied to the region 3, while the region 4 is connected to the ground potential GND (for example 0V). The voltages of the regions 3 and 4 are fixed in the opposite manner in order to program the second bit disposed in the area 5.
In order to read the first bit disposed in the area 6, the region 4 represents a drain region D and the region 3 represents a source region SR. In order to read the second bit stored in the area 5, the cell is read in the opposite direction and the region 4 represents the source region and region 3 represents the drain region.
In order to read the bit stored in the area 6 using a conventional reading technique such as current type sensing, a pre-established reading voltage (for example 9V) is initially applied to the gate G of the cell 1. Following this, a pre-established reading voltage (for example 1.5V–2V) is applied to the region 4, while the region 3 is connected to the ground potential GND (for example 0V). Said potential difference gives rise to a current which passes through the transistors of the bit line selector of the regions 3 and 4, the bit lines themselves, the cell under examination and is detected by a current sense amplifier. The intensity of the current detected, compared to a reference current, makes it possible to distinguish the bit stored in the area 6 of the cell. Conventionally, if the area 6 is without charge, i.e. it is not programmed, the current obtained is greater than the reference current and the stored bit is a logic 1. Vice-versa, if the area 6 is programmed, said current is less than the reference current and the bit stored is a logic 0.
The current reading procedure described is of the static type, but the discussed cell and the circuit solutions which will later be discussed in conjunction with embodiments of the invention are also suitable for dynamic current reading, as can be understood intuitively by the skilled-in-the-art.
In order to erase the bit stored in the area 6, the gate terminal G of the cell 1 is connected the ground potential GND (for example 0V), a pre-established voltage (for example 8V) is applied to the bit line relative to the region 3 leaving the bit line relative to the region 4 unconnected. The same procedure is followed in order to erase the area 5.
It has been noted that, compared to memories made with NOR cells, the path of the current during the reading and programming steps of a NROM cell doubles in length and, consequently, since the total impedance associated with the path increases, the voltage drops also double.
Furthermore, it has been observed that the NROM cells function correctly when, during the reading or programming step, the ground potential is effectively applied to the terminal which acts as source. In other words, in order to program and later read the cell correctly, the potential difference applied between the source and drain terminals of the cells must have a pre-established and controllable value. Concerning this, it has been noted that in conventional NROM memories, conditions may occur in which voltage drops on the current path prevent this from happening, giving rise to a spurious phenomenon called “Chisel effect” during the programming step. Said phenomenon compromises the separation of the charges at the ends of the cell. In fact, with reference to FIG. 1, undesired additional charges are conveyed from the region of channel 2 towards the center of the nitride layer 7. The presence of said charges prevents correct discrimination of the information contained in the cell during reading.